# Sequential Logic Operations in Passive Crossbar Arrays

Passive crossbar memory arrays are the simplest conceivable matrices consisting only of bit and word lines and a storing element, i.e. resistive switch [1], at each junction, resulting in a minimum feature size of 4*F*^{2} [2]. Because of the simple structure, crossbar arrays are easy to fabricate and are excellently applicable for 3D integration [3]. Besides array functionality, logic operations are feasible too [4]. In advantageous approach, two anti-serially connected bipolar resistive switches, complementary resistive switches (CRS), are incorporate at each cross-point junction [5], and allowing memory-in-logic functionality [6].

## BRS and CRS specification

In Fig 1a, the specifications for bipolar restive switches (BRS) and complementary resistive switches (CRS) are depicted. Both devices offer two terminals, labeled with T_{1} and T_{2}, respectively. The logic variables p and *q*, either “0” (low potential) or “1” (high potential) are applied to these terminals. In each case there are two states, *Z* = “1” (cylinder) and *Z* = “0” (cube). In Fig. 1b an exemplary *I-V* characteristic of a BRS cell is depicted. For a positive SET voltage the device switches to state *Z* = “1”, i.e., the low resistive state (LRS), while for a negative RESET voltage the device switches to *Z* = “0”, i.e., the high resistive state (HRS). Fig. 1c shows an exemplary *I-V* characteristics of a CRS cell. Here, *Z* = “1” corresponds to HRS/LRS and *Z* = “0” corresponds to LRS/HRS.

Figure 1: BRS and CRS specifications.

## Readout procedure

In Fig. 2a, the read operation of a BRS cell using a level read scheme is shown. A small read voltage is applied to the cell, and the corresponding read current is detected. A high current (state LRS) is assigned to logical “1” output, while a low current (state HRS) is assigned to a logical “0” output. (b) Read operation of a CRS cell using a spike read scheme. Here, a read voltage pulse which is equivalent to a positive write pulse is applied. Therefore, only if the CRS cell is in state LRS/HRS (cube) the cell switches and a current spike occurs. The occurrence of a current spike is assigned to a logical “0” output, and the absence of a current spike is assigned to a logical “1” output. Due to destructive read-out, a write back step is required.

Figure 2: Read operation of a BRS and CRS device.

## BRS and CRS logic operation

The basic logic operation of a BRS cell (Fig. 3a) and the logic operation of a CRS cell (Fig. 3b) can be understood from a finite state machine representation. The operations are completely identical for both devices. Variable *p* is applied at terminal T_{1} and variable *q* is applied at terminal T_{2}. When starting from state *Z* = “0” the negation of the implication function (*p* NIMP *q*) is realized, while when starting from state *Z* = “1” the reverse implication (*p* RIMP *q*) is conducted. In Fig. 3c the corresponding logical tables are depicted.

Figure 3: Finite state machine representation of BRS and CRS devices, realizing NIMP or RIMP operation.

However, if the previous state *Z*' is not known the actual state is defined by a more general equation (see Fig. 4). Regardless of the previous state *Z*', the cell switches to state *Z* = “1” if T_{1} = “1” and T_{2} = “0” are applied, and to *Z* = “0” if T_{1} = “0” and T_{2} = “1” are applied. For any other input signals, no change of the state variable occurs.

Figure 4: General equation.

Since the logic operation depends on the previous state *Z*', a stateful logic is possible, and in general, a defined initial state *Z*' is needed. Thus, the first logic operations needed are FALSE and TRUE, which must always be performed in a first cycle. The logic tables of TRUE and FALSE are depicted in Fig. 5. To expand the logic functionality *q* and *p* are not applied simultaneously, but sequentially. Hence, the logic operation is provided by a two or three cycle process. With equation from Fig. 4 and either TRUE or FALSE in the first cycle, the implication based operations can be implemented (Fig. 5).

Note that with TRUE (*Z*' = 1) the operation for the next cycle is set to RIMP, while with FALSE (*Z*' = 0) the operation for the next cycle is set to NIMP.

Figure 5: Logic tables for one and two cycle functions.

With a third cycle (Fig. 6), OR, NAND, NOR and AND can be realized, too:

Figure 6: Logic tables for three cycle functions.

Two functions cannot be realized with a single complementary resistive switch or bipolar resistive switch: XOR and XNOR. If these functions are needed, two devices must be connected via a wired AND (“&”).

Note that XNOR and XOR are not required to obtain a functionally complete set of Boolean operators, and it is reasonable to be restricted to 14 of 16 functions for the following reasons:

• only a single device is required for each operation

• the result is inherently stored to memory (state *Z*)

• each cell in a crossbar array can be either used for logic or memory operation

As stated earlier, this systematic approach is valid for both complementary resistive switches and bipolar resistive switches either, but, since no low-ohmic state is present in CRS cells in any step (apart from the reading process), CRS cells are more favorable for crossbar array implementation.

## Conclusion

Using the approach presented here, 14 out of 16 Boolean logic functions can be realized by both, CRS and BRS cells, in at most three cycles and the logic result is directly stored to the memory. For the two remaining logic functions two devices are required. A universal memory, allowing for logic operations in the memory itself, becomes feasible by this approach.

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E. Linn, R. Rosezin, S. Tappertzhofen, U. Böttger, and R. Waser